1. Field of the Invention
The present invention relates to a structure with semiconductor chips embedded therein and a method of fabricating the same, and more particularly, to a structure with the semiconductor chip embedded and the circuit layer integrated therein, and a method of formation thereof.
2. Background of the Invention
Due to the rapid growth in the electronic industry, electronic devices have gradually been developed towards the directions of multi-function, high speed, and high frequency. In the demand of high integration and miniaturization, semiconductor packages have evolved gradually from a single chip ball grid array (BGA) package or flip chip (FC) package to the types of multi-chip package and module package, such as System in Package (SiP), System Integrated Package (SIP) and System in Board (SiB).
These types of multi-chip package and module package are formed by attaching each semiconductor chip on the carrier board one by one using the flip-chip, the wire-bonding, or the SMT techniques. Although these techniques can admit high number of leads, when they perform under high frequency or high speed, the conductive paths may be too long, which limit the electrical efficiency. In addition, since multiple interfaces are required in these conventional techniques, the production cost is increased corresponsively.
Accordingly, to efficiently increase the electrical quality for the electronic devices of the next generation, a method of embedding semiconductor chip in a carrier board to achieve direct electrical connection is often adopted in the industry, so as to reduce the electrical transmission path, thereby reducing the loss of electrical signals and the distortion of the same, and improving the capability of high speed operation.
As shown in FIG. 1, a cross-sectional view of a conventional package with semiconductor chips embedded therein is shown. As shown in the drawing, the package comprises: a carrier board 10, which has at least one opening 100a formed on one surface 100 thereof; at least one semiconductor chip 11 having an inactive surface 11b and an opposing active surface 11a, on which a plurality of electrode pads 110 are formed, and therewith the semiconductor chip 11 received in the opening 100a of the carrier board 10; a built-up structure 12 formed on the carrier board 10, which is electrically connected to the electrode pads 110 of the semiconductor chip 11 through a plurality of conductive vias 120. The inactive surface 11b of the semiconductor chip 11 is attached into the opening 100a of the carrier board 10 via an adhesive 13.
The built-up structure 12 comprises at least one insulating layer 121, at least one circuit layer 122 stacked on the insulating layer 121 and a plurality of conductive vias 120 in the insulating layer 121 to electrically connect the circuit layer 122. The outermost surface of the built-up structure 12 has a plurality of electrical connecting pads 123 and the outermost built-up structure is covered with a solder mask layer 124. The solder mask layer 124 has a plurality of openings for exposing the electrical connecting pads 123, which can be mounted with the solder balls 125.
However, in order to save production cost, a plurality of semiconductor chips are often embedded in a carrier board. Then after a circuit manufacturing completed to form a circuit to thereby extend electrical connections for the semiconductor chip, a cutting process on the carrier board is performed to carry out individual package with a semiconductor chip embedded therein. Nevertheless, in the foregoing method, a space must be preserved in the layout design on the carrier board for the subsequent cutting process using the shaping machine, as a router. Since the shaping machine is relatively large, the preserved space of the carrier board must also be large, thus reducing the usable layout space of the carrier board, and increasing the production cost.
Furthermore, after the semiconductor chip has been embedded in the carrier board following the foregoing method, a process of circuit patterning is carried out on only one surface of the substrate. This makes the two opposing surfaces of the package suffer from unbalanced stresses, thereby causing warpage of the carrier board during the process, as well as reducing product yield.
Moreover, in the conventional process, the shaping machine performs cutting on the carrier board directly, thus the shaping time can not decrease. In addition, as the circuit is made of copper which is highly extensible upon stress exerted by the shaping machine, it may cause scratch of the adjacent semiconductor packages after the cutting process, resulting in damages in the package and reduction in the product yield.
Thus, there is an urgent need for the industry to develop a structure with semiconductor chips embedded therein and a method of fabricating the same, in which the problems such as reduction in usable space of the carrier board, inefficient layout design, substrate warpage, damages in semiconductor package, low product yield, increased cost, and increased time for shaping can be solved.